QRT’s laser evaluation system supports a wide wavelength range from 650 nm to 1650 nm, enabling radiation testing of a variety of semiconductor materials such as silicon (Si), gallium nitride (GaN), silicon carbide (SiC), and devices including memory, processors, and analog components.
However, in special 3D-stacked packages such as HBM (High Bandwidth Memory), the stacked structure prevents laser penetration, making complete evaluation impossible.
Even outside such cases, evaluation feasibility may be restricted depending on the structural characteristics of the package.
A key prerequisite for laser evaluation is decapsulation—removal of the epoxy mold compound from the device. This must be done precisely to maintain accuracy and reliability.
Devices with simple structures (e.g., amplifiers, ADCs, digital isolators) can typically be evaluated from both front and back sides.
However, highly integrated devices such as FPGAs, MCUs, SRAMs, and DRAMs usually require back-side-only evaluation, as the front-side metal layers block laser penetration.
To determine if evaluation is feasible for a given case, it’s best to refer to previously tested examples.
Evaluatable Package Types
Packages with structures like the one below are generally straightforward to decapsulate from both sides, making them suitable for evaluation.
Example of an evaluatable package type
Even within these types, evaluation feasibility may vary depending on the shape and placement of the lead frame.
De-capsulated TSSOP device
Non-Evaluatable Package Types
In packages like BGA, the bottom of the chip is fully bonded to the PCB via solder balls, allowing only top-side decapsulation. This generally makes back-side evaluation impossible.
Example of a non-evaluatable package type (1)
For BGA packages where only the top side can be decapsulated, laser evaluation is often not possible for devices with more than three metal layers (e.g., memory, processors).
However, in some flip-chip BGA packages, the laser can access the underside of the chip, making evaluation feasible.
Because the same chip can be packaged in multiple formats, switching to a more laser-compatible package type can sometimes enable successful evaluation.
Example of a non-evaluatable package type (2)
Preprocessing for Laser Radiation Hardness Testing
The examples above may not offer a definitive answer on whether a specific device is evaluatable.
In most cases, X-ray imaging is used to inspect internal structures beforehand. Below are actual evaluation cases from QRT that may help you assess feasibility in similar situations.
TSSOP Package (Memory, lead frame removal not possible)
Front-side evaluation was blocked by the metal layer. X-ray imaging revealed that the lead frame was connected to multiple pins, preventing back-side frame removal.
However, partial evaluation was performed through exposed areas between lead frames, and potential SEE (Single Event Effects) were successfully detected.
Memory (TSSOP) back side
BGA & TSSOP Packages (Memory)
The original device was in BGA form, but a TSSOP version was acquired. Only back-side decapsulation was possible, and evaluation was conducted successfully from that side.
Memory (TSSOP) back side
BGA Package (Memory)
Although BGA packages are generally difficult to evaluate, this particular flip-chip device allowed back-side laser access, enabling successful evaluation.
Front-side access was still restricted due to the metal layer.
Memory (BGA) back side
TSSOP Package (Memory)
The lead frame fully covered the back of the chip, requiring precise removal. Using detailed X-ray imaging and with support from the manufacturer, removable sections were identified.
Frame removal was performed successfully, exposing over 90% of the back-side die area for evaluation. Front-side evaluation remained blocked by the metal layer.
Memory (TSSOP) back side
SOIC-8 Package (Op-Amp)
This simple SOIC-8 device was easily decapsulated and evaluated from both front and back.
Op-Amp (SOIC) front (left), back (right)
PDIP Package (ADC)
The ADC, housed in a basic DIP package, was also easily decapsulated and evaluated on both sides.
ADC (PDIP) front (left), back (right)
SOIC-8 Package (Digital Isolator, partial lead frame removal)
For the digital isolator, full front-side decapsulation caused damage to the internal coil. Selective decapsulation was performed to avoid interference with the coil.
The back-side lead frame was connected to multiple pins, but careful partial removal enabled evaluation from both sides.
Digital Isolator (SOIC) front (left), back (right)